1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device storing two types of binary number data and an operation method thereof.
2. Description of the Background Art
The recent development in the semiconductor technology is remarkable, which is enabling integration of a large number of circuit elements on a single chip. Also, there exists a great demand for further speeding up the processing speed, and particularly the demand for processing arithmetic operations at high speed is on the increase. As a method of processing arithmetic operations at high speed, use of operating circuits using redundant binary numbers is becoming the object of attention.
General binary numbers in which each digit is expressed using two numbers, that is, 0 and 1, are referred to as binary numbers herein. On the other hand, binary numbers in which each digit is expressed using three numerals, 1, 0 and -1 are referred to as redundant binary numbers. A binary number having n bits is generally represented as x.sub.n x.sub.n-1 . . . X.sub.1. Herein, a binary number by binary representation without a sign is represented as [x.sub.n x.sub.n-1 . . . x.sub.1 ].sub.2, and a binary number by the 2's complement representation is expressed as [x.sub.n x.sub.n-1 . . . x.sub.1 ].sub.c2. In this case, each of x.sub.n, x.sub.n-1, . . . , x.sub.1 represents 0 or 1. A redundant binary number is expressed as [x.sub.n, x.sub.n-1, . . . x.sub.1 ].sub.SD2. In this case, each of x.sub.n, x.sub.n-1, . . , x.sub.1 represents 1, 0 or -1.
In the binary representation, a decimal number "3" is expressed as [011].sub.2. On the other hand, in the redundant binary representation, the decimal number "3" is represented as [0, 1, 1].sub.SD2 or [1, 0, -1].sub.SD2. Thus, in the redundant binary representation, a numeral can be represented in plural ways.
The mutual conversion between binary numbers and redundant binary numbers is described in "A VLSI-Oriented High-Speed Multiplier Using a Redundant Binary Addition Tree", Papers of the Institute of Electronics and Communication Engineers of Japan, June 1983 Vol. J66-D No. 6, pp. 683-690 by Takagi, Yasuura and Yajima, for example.
A binary representation coincides with one of redundant binary representations. For example, a binary representation [011].sub.2 coincides with a redundant binary representation [0, 1, 1].sub.SD2. Accordingly, no processings are required in order to convert a binary number into a redundant binary number.
On the other hand, conversion from a redundant binary number into a binary number can be performed by subtraction of two binary numbers One binary number is obtained by setting bits corresponding to digits of "1" in a redundant binary number to "1" and setting remaining bits to "0". The other binary number is obtained by setting bits corresponding to digits of "-1" in a redundant binary number to "1" and setting remaining bits to "0". Subtracting the other binary number from the one binary number, a binary number by the 2's complement representation is obtained.
For example, a redundant binary number [1, 0, -1].sub.SD2 is converted into a binary number [0 1 1].sub.C2 as described below. EQU [1, 0, -1].sub.SD2 =[100].sub.2 -[001].sub.2 =[011].sub.C2
Subtraction of two binary numbers is performed by addition using binary numbers by 2's complement representation. Accordingly, conversion from a redundant binary number into a binary number is mainly made using an adder circuit.
In operation using binary numbers, a delay occurs due to propagation of carry signals, so that the operation time increases as the data bit length increases. On the other hand, a single number can be represented in plural ways in the redundant binary number representation, so that the number of times of carrying can be reduced. Addition and multiplication using redundant binary numbers are described in the above-identified Papers of the Institute of Electronics and Communication Engineers of Japan.
An example of simple addition is now described. When performing an addition 3+1=4 using binary numbers, as shown in FIG. 10, a carry is generated from the least significant bit to the second bit and further a carry is generated from the second bit to the third bit. On the other hand, as shown in FIG. 11, a decimal number "3" is expressed as a redundant binary number [1, 0, -1].sub.SD2 and a decimal number "1" is expressed as a redundant binary number [0, 0, 1].sub.SD2. In such addition as using redundant binary numbers, a carry is not generated. Accordingly, use of redundant binary numbers enables high speed operation.
A large number of circuit elements are required in an operation circuit using redundant binary numbers, but it does not a matter because of the recent development in the semiconductor technique. Accordingly, an operation circuit using redundant binary numbers and having high speed performance are incorporated in a semiconductor integrated circuit device. An operation circuit using redundant binary numbers is disclosed in Yamashita et al., "A 200 MHz 16-bit BiCMOS Signal Processor", 1989 ISSCC DIGEST OF TECHNICAL PAPERS., pp. 172-173 and Edamatsu et al., "A 33MFLOPS Floating Point Processor Using Redundant Binary Representation", 1988 ISSCC DIGEST OF TECHNICAL PAPERS, pp. 152-153, for example.
As described above, high speed operation circuits using redundant binary numbers are in development. However, in most data processing systems, binary number data are employed. Accordingly, mutual conversion is required between a redundant binary number and a binary number for connecting an operation circuit using redundant binary numbers to other systems. Accordingly, a binary number adder circuit is necessary as described and the operation time increases because of the conversion.
Especially, in normal microprocessors, arithmetic operation processes and logic operation processes are performed related to a large amount of data. The arithmetic operation processes can be performed using redundant binary number data but the logical operation processes cannot be performed using redundant binary number data.
In FIG. 12, a general microprocessor, mainly its execution unit, is shown. A microprocessor 300 includes a register file circuit (RF) 310 and an operation process circuit (Arithmetic Logic Unit ALU) 320. A main memory device 200 is connected to the microprocessor 300. Microprocessor 300 is formed of a single LSI and main memory device 200 is formed of another LSI. Binary number data is stored in main memory device 200. Operation processing circuit 320 performs operation processes such as arithmetic operation processes, logical operation processes and so forth. Register file circuit 310 is formed of a normal RAM (Random Access Memory) which stores data necessary in processings by operation processing circuit 320 in the data stored in main memory device 200.
Now, assuming that an operation circuit is used which is capable of operation utilizing redundant binary numbers and mutual conversion between a redundant binary number and a binary number, the operation in that case is described.
First, binary number data required for operation processing by operation processing circuit 320 is transferred from main storage 200 to register file circuit 310, where the data is stored. When executing an instruction of adding two numbers, for example, two pieces of binary number data are transferred from main storage 200 to register file circuit 310.
Next, operation processing circuit 320 executes a process of adding the two pieces of data. Since binary number data can be regarded as redundant binary number data, operation processing circuit 320 executes operation utilizing redundant binary numbers in this case. The operation time is thus reduced A result of the operation is redundant binary number data.
Usually register file circuit 310 cannot store redundant binary number data. Accordingly, operation processing circuit 320 converts redundant binary number data into binary number data. The converted binary number data is stored in register file circuit 310. In this case, operation processing circuit 320 is required to perform a conversion process in addition to the operation process, so that a long execution time is required after all.
If it is assumed that register file circuit 310 can store redundant binary number data, the operation result is stored in register file circuit 310 in the form of a redundant binary number. If an instruction utilizing the operation result next is an instruction of arithmetic operation, the operation can be executed utilizing the redundant binary number data.
If an instruction utilizing the operation result next is an instruction of logical operation, however, the redundant binary number data must be converted into binary number data. In that case, operation processing circuit 320 must perform the conversion processing, resulting in an increase in the execution time.
Furthermore, even if no instructions of logical operation exist, the redundant binary number data stored in register file circuit 310 is reserved in main memory device 200 finally. Main memory device 200 is also connected to other circuits in the system, so that data must be necessarily stored in the form of binary numbers. Accordingly, redundant binary number data stored in register file circuit 310 is transferred to main memory device 200 after converted into binary number data by operation processing circuit 320.
Thus, extra time is taken for converting redundant binary number data into binary number data, resulting in low execution speed. Accordingly, it is not done actually to incorporate an operation circuit utilizing redundant binary number data into a microprocessor.
However, great demands exist for further speeding up microprocessors by performing arithmetic operations with redundant binary numbers.